FIG. 1 shows the conventional video input level control circuit comprising a video input circuit 71 for amplifying a video signal inputted from a video card mounted on a PC 70 to a predetermined level; a video output amplifying section 73 for amplifying the video signal outputted from the video input circuit 71 to a predetermined output level, and outputting the amplified signal to a cathode ray tube (CRT) 72; and a video input level control section 74 for controlling an input level of the video signal inputted from the video output amplifying section 73 to the CRT 72.
The video output amplifying section 73 comprises a buffer transistor Q1 for buffering the video signal inputted from the video input circuit 71, and amplifying transistors Q2, Q3 for cascode-amplifying the video signal outputted from the buffer transistor Q1.
A base terminal of the amplifying transistor Q2 is connected to an emitter terminal of the buffer transistor Q1, and the emitter terminal of the amplifying transistor Q2 is connected to the collector terminal of the amplifying transistor Q3. Bias voltages Vcc1, Vcc3 are connected to the collector terminal of the transistors Q1, Q2 via resistors R1, R3. A bias voltage Vcc2 is connected to the base terminal of the amplifying transistor Q2, and CRT 72 is connected to the collector terminal of the amplifying transistor Q3. Resistors R2, R4 are connected to the emitter terminal of the transistors Q1, Q3, respectively.
The video input level control section 74 comprises a detecting transistor Q4 connected to the base terminal of the buffer transistor Q1 via resistor R5 for detecting abnormality of the video input level and switch-amplifying the detected video input level; a thermistor TH1 connected to the base terminal of the detecting transistor Q4 for detecting internal temperature of the product; a switching transistor Q5 connected to the collector terminal of the detecting transistor Q4 for controlling the emitter voltage level of the amplifying transistor Q3; and a transistor Q6 connected to the collector terminal of the switching transistor Q5 for controlling switching intervals of the switching transistor Q5.
The emitter terminal of the amplifying transistor Q3 is connected to the collector terminal of the switching transistor Q5 via the resistor R4, and the collector terminal of the transistor Q6 is connected to the collector terminal of the detecting transistor Q4. A capacitor C1 and a resistor R11 are connected in parallel to the emitter terminal of the transistor Q6. A bias voltage Vcc4 is connected to the collector terminal of the detecting transistor Q4 via a resistor R7, and the bias voltage Vcc4 is connected to the emitter terminal of the detecting transistor Q4 via a resistor R10 for setting a bias voltage level. A resistor R13 is connected to the base terminal of the transistor Q6.
The transistors Q1-Q4 and Q6 are NPN-type transistors, and the transistor Q5 is a PNP-type transistor.
The conventional video input level control circuit constituted above operates as follows.
If a video signal is inputted to the video input circuit 71 from the video card of the connected PC 70, the video input circuit 71 amplifies the inputted video signal to a predetermined level. Then, the video input circuit 71 inputs the amplified video signal to the base terminal of the buffer transistor Q1 of the video output amplifying section. Subsequently, the buffer transistor Q1 buffers the inputted video signal and inputs the buffered video signal to the base terminal of the amplifying transistor Q3. The amplifying transistor Q3 is then turned on, and the amplifying transistor Q2 is subsequently turned on. The video signal is cascode-amplified by these two transistors Q2, Q3, and inputted to the CRT 72. CRT 72 then displays an image according to the inputted video signal.
The video signal of the video input circuit 71 is also inputted to the base terminal of the detecting transistor Q4. Since the emitter standard voltage Ve of the detecting transistor Q4 is set to be bias voltage Vcc4 by the resistor R10, the base voltage Vb=0.7+Ve. Therefore, the detecting transistor Q4 is turned on only at the voltage higher than the base voltage. In other words, if the video signal input level is applied to the CRT 72 as a normal voltage level, e.g., 0.7 V, the detecting transistor Q4 is not turned on. Accordingly, neither the switching transistor Q5 nor the transistor Q6 is turned on, thereby never affecting the emitter voltage level of the amplifying transistor Q3.
However, if the video signal input level is applied to the CRT 72 at an abnormal level, e.g., high, or if an internal temperature of the product increases, the voltage level at the base terminal of the detecting transistor Q4 becomes higher than Vb=0.7+Ve. In other words, if the internal temperature of the product affecting the video input level increases, the internal resistance of the thermistor TH1 becomes greater, and consequently, the bias voltage Vcc4 at the base terminal of the detecting transistor Q4 becomes higher than Vb=0.7+Ve after passing through the thermistor TH1. In another case, if the video signal input level inputted through the video input circuit 71 is higher than the normal level, the video signal is applied to the base terminal at a voltage higher than the base voltage of the detecting transistor Q4. Accordingly, the detecting transistor Q4 is turned on since the voltage level at the base terminal becomes higher than the standard voltage level Vb=0.7+Ve. The bias voltage Vcc4 flowing to the base terminal of the switching transistor Q5 subsequently changes its flow to the detecting transistor Q4. The switching transistor Q5 is turned on as a consequence.
If the switching transistor Q5 is turned on, the collector voltage level at the switching transistor Q5 becomes higher, and the emitter voltage level at the collector terminal of the switching transistor Q5 subsequently becomes higher. As a consequence, the amplification ability of the amplifying transistors Q2, Q3 deteriorates, and the video input level applied to the CRT 72 can be automatically controlled.
If the switching transistor Q5 is turned on, the transistor Q6 is subsequently turned on, and controls operation of the detecting transistor Q4. As shown in FIG. 2A, the detecting transistor Q4 recognizes the video signal which is as high as the base voltage as a starting signal, and operates imperfectly during the interval T1, as shown in FIG. 2B. The transistor Q6 is turned on only while the capacitor C1, which is discharged through the resistor R11 having a great resistance value, is charged. While the transistor Q6 is turned on, the voltage at the emitter of the detecting transistor Q4 flows to the transistor Q6, thereby lowering the voltage level of the emitter of the detecting transistor Q4. Therefore, the detecting transistor Q4 operates only while the transistor Q6 is turned on. Thus, the turning-on interval of the detecting transistor Q4 is determined by the interval of the capacitor C1. The interval of the capacitor C1 is short as shown to be T1 in FIG. 2C. Accordingly, the video output level inputted to the CRT 72 rapidly becomes lower, and brightness of the screen can be controlled to be minimal.
The conventional video input level control circuit constituted above is thermally stable and can compensate the varied portion if the video input level becomes higher than a predetermined level. If the video input level becomes lower than the standard input level due to different types of video cards of the PC 70, the varied portion cannot be compensated, thereby excessively saturating the video signal and deteriorating quality of the screen.